1. Field of the Invention
The present invention relates generally to controlling access to a memory which is shared by multiple controllers, such as a memory shared by a graphics controller and a system controller.
2. State of the Art
As memories become increasingly more dense, memory control required to efficiently use memory space has become more sophisticated. For example, a document entitled "Cache and Memory Design Considerations For The Intel 486.TM. DX2 Microprocessor", by Taufik T. Ma dated January, 1992, describes the use of a paged memory system wherein storage areas of the memory are divided into separate pages. As described in the Ma document, data is formed into double words, or "Dwords", which can each consist of, for example, 32 bits. In a memory formed with 512 rows and 512 columns, each row can be considered a page of the memory for storing multiple Dwords.
A paged memory system allows for enhanced speed in back-to-back read or write cycles. Back-to-back cycles occur when multiple accesses to the memory are made, with sequential storage areas in the memory being written during consecutive access cycles. To realize the benefits associated with organized memories, access to these memories has been limited to a single memory controller. Organized memories have not been used as shared memories, because any arbitration scheme used to arbitrate memory access among multiple controllers would undermine the efficiencies which the organized memory was created to provide.
Accordingly, it would be desirable to use an organized memory, such as a paged memory, as a shared memory which can be accessed by multiple controllers. In so doing, it would be desirable to assign each of the controllers a hierarchical priority in accessing the memory without detrimentally affecting the efficiencies associated with the use of an organized memory.